The AD is a numerically controlled oscillator The AD offers the user a variety of output .. may not meet the specifications listed in the data sheet. AD evaluation board (EVAL-CNSDZ) is designed to help customers in the AD data sheet available from Analog Devices and should be. Part Number: AD, Maunfacturer: Analog Devices, Part Family: AD, File type: PDF, Document: Datasheet – semiconductor.
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The DAC output should be filtered appropriately before being applied to the comparator to improve jitter.
The load resistors can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth.
Consideration must be given to the relationship of the selected output frequency and the reference clock frequency to avoid unwanted output anomalies.
AD Datasheet(PDF) – Analog Devices
Other models listed in the table may still be available if they have a status that is not obsolete. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD Output Compliance The output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications.
The frequency registers are 28 bits; with a 75 MHz clock rate, resolution of 0. Refer to Table Most orders ship within 48 hours of this date.
Good decoupling is important. This resets appropriate internal registers to 0 to provide an analog output of midscale. Select the purchase button to display inventory availability and online purchase options.
This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. Control Register DB15 0 Rev. The power supply lines to the AD should use as large a track as possible to datasheett low impedance paths and reduce the effects of glitches on the power supply line.
20 mW Power, 2.3 V to 5.5 V, AD9834 Data Sheet
An on-board regulator steps down the voltage applied at DVDD to 2. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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The SFDR refers to the largest spur or harmonic present in the band of interest. The output from the DAC can be filtered externally before being applied to the comparator input. The comparator datssheet accept signals in the range of approximately mV p-p to 1 V p-p. View Detailed Reference Design Information.
The various ranges specified are as follows:. The different functions and the various output options ax9834 the AD are described in more detail in the Frequency and Phase Registers section. RESET does not affect any of the datasheett registers. The effect of asserting the SLEEP pin is evident immediately at the output, that is, the zero-to-one transition of this pin is not sampled. Temperature Range This is the acceptable operating range of the device.
AVDD can have a value from 2.
Please Select a Region. This square wave can also be divided by two before being output. Capability for phase modulation and frequency modulation is provided. ADIsimDDS uses mathematical equations to model and illustrate the overall performance of the selected device.
This tool also models an estimate of the overall spectral performance, and allows the user to explore the effects of external reconstruction filters. The device operates with a power supply from 2. The timing diagram for this operation is given in Figure 5. Package Description The package for this IC i.
It is necessary only to have sufficient phase resolution such that the errors due dtaasheet truncation are smaller than the resolution of the bit DAC. The accumulator simply scales the range of phase numbers into a multibit digital word. AD 11 m W Power, 2.